1. Field of the Invention
The present invention relates to a method and apparatus for managing peripheral clocks.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Shown in FIG. 1 is a typical general purpose computer system 10. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit chip. The Related Application 1 discloses several circuits adapted to operate in the sub-threshold domain.
Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 12 comprising: a central processing unit (“CPU”) 14; at least one random-access memory (“RAM”) facility 16; at least one Flash memory (“Flash”) facility 18; one or more timers (“Timers”) 20; at least one input/output master (“I/O Master”) facility 22; at least one input/output slave (“I/O Slave”) facility 24; at least one analog to digital converter (“ADC”) facility 26; a power management unit (“PMU”) 28; and a clock generator (“Clock Generator”) facility 30. A system bus (“System Bus”) 32 interconnects the several MCU facilities 14-30, and a clock distribution bus (“Clock Bus”) 34 distributes all clock signals developed by the Clock Generator 30 to the respective clocked facilities. As is known, development of the several clocks is generally controlled by information written to one or more control registers within Clock Generator 30 via the System Bus 32, and by system power state information typically provided by the PMU 28.
A typical prior art Clock Generator 30, as illustrated in FIG. 3, includes several oscillators, OSC1 to OSCn, and develops a number of clocks, Clock1 to Clockm, for the system facilities 14-28. In a typical MCU 12, there will be a relatively small number n of oscillators, e.g., from 2 to 5, and a relatively larger number m of clocks generated, e.g., from 5 to 20. During normal operation, a control (“Control”) facility 36 selects as the source of each clock one of the oscillators via a respective one of m multiplexors (“MUXs”); and in some cases may include a divider of the oscillator output. Depending on the requirement of each particular clocked facility 14-28, some or all of the clocks may be gated via respective gates (“Gates”) in order to reduce power. In the illustrated embodiment, each of the oscillators is adapted selectively to be enabled and disabled, providing further potential power reduction. All of the selection, gating and enabling is managed by Control 36, which may have registers which can be changed by software over the System Bus 32, and which, as in the illustrated embodiment, receives information about the system power state from the PMU 28.
As is know, the MCU 12 exists in one of several power states at any particular time, with the objective of using the least possible power at all times. These power states typically fall into two main categories: running when the processor is operating and its clock is active; and sleeping when the processor is not operating and its clock is not active. There are often different states within each category. There may be different sleeping states depending on whether the oscillator which is used to generate the CPU 14 clock is enabled or not, and different running states depending on which clocked facilities are active and, in general, current system activity.
Typically, software running on the CPU 14 initiates the transition from a “running” state to a “sleeping” state; whereas the transition from a “sleeping” state to a “running” state is typically initiated by a hardware event, most commonly the reception of an interrupt from an internal facility or an external device. Software selects between multiple different states within each power state category to determine the current “running” state and the “sleeping” state. This architecture is straightforward in that software running on the CPU defines the power states, and therefore which oscillators and clocks are enabled at any point in time.
A challenge in the above architecture is that the particular running power states can only be changed while the CPU 14 is executing software. There are two major areas where this approach results in high power consumption:                1. The CPU 14 (which requires the memory facilities to also be running) is a major source of power consumption. Thus changes to the power states (other than the transition from the currently selected “sleeping” state to the currently selected “running” state due to an interrupt) can only occur in a high power environment.        2. In many cases an internal or external event requires a change in the power state, which requires that an interrupt be generated, the CPU 14 enters its high power, active state, and makes the desired changes to the power states (enabling or disabling an oscillator, for example), and then the CPU 14 returns the system to the “sleeping” state. This typically keeps the system in a high power state for some time.        
In addition to the power implications, this prior art approach also creates functional complexity because selecting and enabling the appropriate clock for a clocked facility requires interaction with the power state functions in the Clock Generator 30. The typically requires the definition of a large number of power states with different clocks and oscillators enabled in each one. As a result, there is a tendency to leave clocks enabled as a safe default state which also contributes to higher power.
What is needed is a method and apparatus adapted selectively to develop the several system clocks while consuming less power than known prior art.